Wafer Dicing & Preparation | Ultra-Thin Semiconductor Processing with High Precision

Overview

This stage processes the completed wafer into individual dies (chips) suitable for packaging and testing.

Back Grinding

Purpose: In semiconductor wafer fabrication, the initial thickness of a wafer typically exceeds 700μm. To meet the stringent requirements for thickness, heat dissipation, and form factor, wafers must undergo a thinning process. The wafer is typically reduced to a thickness of 100-150μm, and in some cases, even thinner. This thinning enhances thermal performance by improving heat dissipation, reduces package size, enhances mechanical flexibility, and minimizes signal delay—key factors for high-performance semiconductor applications.
Technical Challenges:
- Stress and Warpage: Mechanical stress from the back grinding process may cause wafer warpage or micro-cracking.
- Handling Ultra-Thin Wafers: The thinner the wafer, the higher the risk of breakage during subsequent handling and processing.
- Damage Layer Management: Mechanical grinding inevitably induces damage to the wafer’s surface and sub-surface, requiring additional steps to eliminate.
BIWIN’s Process Capabilities:

Capabilities

Key Metrics/Parameters

BIWIN Performance

Thickness Uniformity

Total Thickness Variation (TTV, µm)

<3

Surface Roughness

Surface Roughness (Ra, µm)

<0.06

Minimum Thickness

Thickness of Ultra-Thin Wafers (µm)

<25

Stress Control

Stress (mPa)

＞450

Yield

Overall Grinding Yield (%)

>99.9

Wafer Dicing

Purpose: Wafer dicing is the process of cutting or sawing the thin silicon wafers into their respective parts, known as dies.
Technical Challenges:
- High Precision and Low Damage: Precise and accurate dicing ensures that the delicate structures within the semiconductor devices remain intact, preserving their functionality. As the blade cuts through the wafer, it generates mechanical stress, which can lead to chipping, cracking, or deformation of the delicate structures of the circuitry within the chip.
- Wafer Warpage: Thinning the wafer can induce the wafer to warp, increasing the difficulty and inconsistency of the cutting process.
BIWIN’s Process Capabilities:

Capabilities

Key Metrics/Parameters

BIWIN Performance

Thickness Control

Applicable Wafer Thickness Range (μm)

＞50

Kerf Width Control

Kerf Width (μm)

＞50

Chipping Control

Front/Back Side Chipping (μm)

<15

Yield

Overall Dicing Yield (%)

>99.99

Laser Grooving

Purpose: When working with fragile materials such as Low-kdielectrics, the laser grooving process is employed to prepare the wafer for precise cutting. This two-step process begins with the laser creating fine grooves along the cutting path, effectively isolating the fragile material. The grooves are then followed by a diamond-blade cutting through the silicon wafer. This technique prevents issues commonly associated with blade dicing, such as Low-k film delamination, chipping, and subsurface cracking.
Technical Challenges:
- Heat-Affected Zone (HAZ) Control: The laser’s thermal effects can cause local material melting or micro-cracks. Precise control of laser parameters (like energy, wavelength, and pulse duration) is necessary to minimize thermal damage.
- Precision and Consistency: Accurate positioning of the grooves and consistent depth are critical. Any inaccuracies can affect the subsequent yields and results.
BIWIN’s Process Capabilities:

Capabilities

Key Metrics/Parameters

BIWIN Performance

Thickness Control

Applicable Wafer Thickness Range (µm)

＞50

Groove Width

Minimum Groove Width (µm)

>50

Heat-Affected Zone Control

Heat-Affected Zone around Groove (µm)

< 5

Groove Depth

Typical Groove Depth (µm)

>10

Positioning Accuracy

Repeated Positioning Accuracy (μm)

±1.5

Yield

Overall Laser Grooving Yield (%)

>99.99

Stealth Dicing

Purpose: Stealth Dicing technologyfocuses the wavelength of a laser beam to permeate materials, creating a modified layer instead of directly ablating the material. An external force is applied to a wafer by uniformly tensing the tape in the peripheral direction through tape expansion. This technique achieves a dust-free,low-stress, high-quality dicing on the device, particularly for ultra-thin wafers.
Technical Challenges:
- Laser Parameter Optimization: The process requires highly precise control of laser parameters such as wavelength, pulse energy, focus depth, and accuracy to ensure the modified layer is formed within the wafer without damaging the surface circuitry.
- Wafer Warping and Height Control: Wafer warpage can disrupt the laser focus, affecting the accuracy and quality.
BIWIN’s Process Capabilities: