Package Assembly for Semiconductors | Precision Marking, Ball Mounting & Singulation

Overview

The package assembly is a pivotal stage where the bare silicon die is electrically and mechanically connected to the package’s external structure.

Purpose: Unit marking involves engraving product details (model numbers, specifications, production batch numbers, trademarks, etc.) onto the surface of the package using lasers (or other printing methods) for traceability and identification.
Technical Challenges: The marking must be clear, durable, and not damage the package or the internal chip. Improper laser parameters may lead to excessive material ablation or unclear markings.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Marking Accuracy	Minimum Character Height (mm)	0.2
Marking Accuracy	Minimum Line Width (μm)	< 20
Barcode	Supported Barcode Formats	Full Support (QR, Data Matrix, etc.)
Barcode	Minimum Data Matrix Size (mm)	0.5 × 0.5
Material Compatibility	Epoxy Molding Compound (EMC)	Excellent
Material Compatibility	PCB Solder Mask	Excellent
Dust Control	Particles Generated During Marking	< 100 particles/cm³
Yield	Overall Unit Marking Yield (%)	>99.99

Purpose: Lid marking involves engraving product details (model numbers, specifications, production batch numbers, trademarks, etc.) onto the surface of the heat dissipation cover for traceability and identification.
Technical Challenges: The marking must be clear, durable, and not damage the package or the internal components. Improper laser parameters may lead to excessive material ablation or unclear markings. The material properties must be considered to avoid damage to the heat dissipation cover or affect its performance.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Accuracy	Laser Marking Accuracy (mm)	±0.05
	Depth Consistency (μm)	1±0.5
	Minimum Character Spacing (μm)	0.06
	Minimum Character Height (μm)	0.55
Yield	Overall Lid Marking Yield (%)	>99.99

Purpose: BGA assembly is a process of mounting and connecting ball arrays onto the package substrateto establish the connection between the chip and the PCB.
Technical Challenges: Ensuring consistent size, coplanarity, and reliability in solder ball mounting is crucial. Variations in ball size or position can lead to poor soldering on the PCB.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Accuracy	Minimum Solder Ball Diameter (μm)	< 150
	Minimum Solder Ball Pitch (μm)	< 350
	Accuracy (μm, @3σ)	± 10
Warpage Control	Maximum Substrate Warpage (mm)	<15
Yield	First Pass Defect Rate (ppm)	< 20

Purpose: Flip Chip Single-Ball Balling involves accurately forming solder bumps(balls) during flip-chip (FC) bondingor when a single chip requires ball mounting.
Technical Challenges: The process requires high precision for ball height, diameter, and composition. Any deviation could compromise interconnection reliability and electrical performance.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Accuracy	Minimum Solder Ball Diameter (μm)	＞180
	Minimum Solder Ball Pitch (μm)	＞ 400
	Accuracy (μm, @3σ)	±30
Warpage Control	Maximum Substrate Warpage (mm)	<200
Yield	First Pass Defect Rate (ppm)	< 20

Purpose: In the package manufacturing process, dicing is performed to divide the wafer into individual chips in a hexahedral shape. Such individualization of a wafer to multiple chips is known as “Singulation”.
Technical Challenges: Accurate alignment is essential to avoid damaging the package or internal circuitry during the singulation. The mechanical stress and debris generated when dicing may affect the overall dicing quality.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Accuracy	Kerf Width (μm)	< 150
Accuracy	Position Accuracy (μm, @3σ)	±30
Chipping Control	Top Surface Chipping (μm)	< 15
	Sidewall Chipping (μm)	< 20
	Solder Ball Damage (BGA Packaging)	None Visible Damage
Yield	Overall Singulation Yield (%)	>99.99