Chip Interconnection and Protection

Overview

This stage packages the qualified die (Known Good Die or KGD) into an independent unit with functioning protection, connectivity, and heat dissipation.

Die Attach

Purpose: A die bonding technique, a die (IC chip) is attached to the die pad of a semiconductor package’s support structure, such as a substrate or a lead frame.
Technical Challenges: Voids and uniformity in the die attach layers are critical and can directly impact heat dissipation and mechanical strength. Mismatched Coefficients of Thermal Expansion (CTE) between the silicon die can cause excessive mechanical stress for larger dies.
BIWIN’s Process Capabilities:

Capabilities

Key Metrics/Parameters

BIWIN Performance

Process Accuracy

Process Accuracy (μm)

±10

Die Size Compatibility

Die Size

Full Range

Rotational Control

Die Tilt Angle (°)

< 0.1

Stacked Die Layers

Number of Stacked Die Layers

>32

Thickness Control

Ultra-Thin Die Handling (μm)

>25

Substrate Thickness

Ultra-Thin Substrate Thickness (μm)

>70

Yield

Overall Die Attach Yield (%)

>99.99

Interconnect Process

Wire Bonding
- Purpose: Wire bonding creates electrical interconnections using bonding wires,fine wires made of materials such as gold and aluminum, placed between the bonding pad on the die to the substrate.
- Technical Challenges: This process requires precise control ofthe applied force, processing time, and parameters to prevent poor connections or chip damage. The increasing pin counts and layout densities may lead to electrical short circuits or interference.
BIWIN’s Process Capabilities:

Capabilities

Key Metrics/Parameters

BIWIN Performance

Bonding Accuracy

Bonding Accuracy (μm)

±3

Wire Diameter Range

Wire Diameter (μm)

15-50 (Gold/Copper/Alloy)

Pad Size

Minimum Pad Size (μm)

<35

Overhang

Maximum Overhang (μm)

＜1500

Wire Arc Control

Minimum Wire Arc Height (μm)

>25

Yield

Overall Wire Bonding Yield (%)

>99.9

Flip Chip

Purpose: Flip chip, also known as “controlled-collapse chip connection” (C4), is an advanced semiconductor packaging technique for the direct attachment of a semiconductor chip to a substrate. In flip chip technology, the active side of the chip faces downward, and electrical connections are made through conductive
Technical Challenges: Bump fabrication and coplanarity control require high precision. The substrate’s latness and line accuracy requirements are far more stringent than those for wire bonding.

BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Bump Process and Density	Type	Solder Ball/Copper Pillar/Microbump
	Diameter (μm)	＞40
	Pitch (μm)	＞70
Process Accuracy	Accuracy (μm, @3σ)	± 5
Mass Production and Yield	Overall Flip Chip Yield (%)	>99.98%

Underfill

Purpose: Underfill is an epoxy material that fills gaps between a chip and the PCB substrate. Underfill dissipates stress throughout the package, alleviates stress on solder balls to increase reliability under high fatigue cycle applications. Underfill materials provide mechanical reinforcement that prevents potential reliability issues caused by environments.
Technical Challenges:
- Voids and Filling Defects: Voids caused by outgassing, air entrapment between the solder and underfill during the reflow process, negatively impact reliability.
- High Precision and Uniformity: As the pitch of the solder bumps becomes finer, there are increasingly stringent demands on the flowability, wettability, and accuracy of the underfill resin.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Dispensing	Dispensing Accuracy	±20
	Capillary Height	Die Edge ≥70% Die Corner ≥50%
	Overflow Width (μm)	Dispensing Edge >450 Overflow Edge >250
	Bump Gap (μm)	＞40
	Chip Gap (μm)	＞100
	Underfill Void Rate (%)	<1%
Yield	Overall Underfill Yield (%)	>99.98%

Lid Attach

Purpose: Lid attach enhances heat dissipation and protects the fragile die and wire bonds inside the package from environmental factors, as well as from physical damage. It’s commonly used in packages such as FCBGA.
Technical Challenges: The lid requires superior contact to avoid air gaps that could reduce heat dissipation.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Process Accuracy	X/Y Direction (μm)	±50
	Lid Flatness (μm)	< 100
	TIM (Thermal Interface Material) Thickness (μm)	20 – 90
	TIM Void Rate (%)	< 1
Yield	Overall Lid Attach Yield (%)	>99.99

Molding

Purpose: Using epoxy molding compound (EMC), the chip and lead frame are encapsulated to provide mechanical protection, heat dissipation, and prevent environmental corrosion.
Technical Challenges: Mismatch in the thermal expansion coefficients between the molding compound, chip, and substrate can cause internal stresses, potentially leading to package warpage or interface delamination. Uneven flow during the molding process may result in defects such as voids or incomplete filling.
BIWIN’s Process Capabilities: