Semiconductor Testing & Verification | Burn-In, ATE & System-Level Testing

Overview

BIWIN provides a complete range of tests to verify the functionality, performance, and reliability of every chip.

Purpose: The Burn-In Test subjects ICs to prolonged stress testing under high temperatures and voltages to identify any potential defects in the ICs, ensuring the reliability and lifespan of shipped products.
Technical Challenges: The test is costly and time-consuming, requiring precise control of test conditions and efficient management of heat dissipation during testing.
BIWIN’s Testing Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Temperature Control	Maximum Test Temperature (°C)	150
Voltage Stress	Temperature Uniformity (°C, in-chamber)	±2
Voltage Stress	Voltage Precision (%)	±1%
Parallel Capability	Maximum Number of Chips per System	>6,000
Parallel Capability	Support Wafer-Level Burn-In (WLBIT)	No
Test Duration	Typical Duration of Dynamic Burn-In Test (hrs)	48 – 168
Yield	Overall Burn-In Yield (%)	>99.5
Test Type	Support Static/Dynamic Burn-In Test	Full Support
Test Type	Test During Burn-In Capability	Yes

Purpose: Automated Test Equipment (ATE) is a computerized machinery that rapidly and comprehensively verifies the functionality and measures the electrical characteristics, like DC and AC parameters, to meet the desired specifications.
Technical Challenges: Developing the test programs can be complex, and the testing time directly impacts costs and capacity. As chip speeds and complexity increase, ATE systems must meet higher demands for speed, channel count, and accuracy.
BIWIN’s Testing Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Test Precision	Overall Time Accuracy (ps)	<111
Test Precision	Voltage Precision (%)	±0.5%
Yield	Overall Test Yield (%)	>99.5
Yield	Defect Rate (ppm)	<100
Test Coverage	Test Types (Function, Parameters, Reliability)	Full Support
Test Coverage	Supported Protocols (DDR5, PCIe Gen6, LPDDR5, etc.)	Full Support
Reliability Testing	Maximum Test Temperature (°C)	125
Reliability Testing	Temperature Uniformity (°C, In-Chamber)	±3

Purpose: System-Level Test (SLT)validates the performance and reliability of integrated circuits (ICs) in real-world application conditions (e.g., installed on a motherboard). SLT addresses any gaps in coverage from ATE tests to real-world scenarios.
Technical Challenges: Developing an SLT system is complex and costly, with testing efficiency typically lower than that of ATE systems. Effectively replicating various application scenarios and fault modes is are major challenge.
BIWIN’s Process Capabilities:

Capabilities	Key Metrics/Parameters	BIWIN Performance
Test System	Maximum Number of Chips per System	256
Test System	Protocols (DDR, LPDDR, PCIe, UFS, etc.)	Full Support
Environmental Control	Temperature Range (°C)	25°C to +85°C
Environmental Control	Temperature Uniformity (°C, in-chamber)	±2
Yield	Overall SLT Yield (%)	>99.5
Yield	Defect Miss Rate (ppm)	<100
Test Coverage	Test Types (Function, Performance, Compatibility, Reliability)	Full Support
Test Coverage	Supported Storage Types (DRAM, NAND, NOR, etc.)	Full Support