Failure Analysis (FA)

Failure analysis during the semiconductor packaging process is a systematic and precise diagnostic procedure aimed at locating defects, analyzing mechanisms, and identifying root causes to improve yield and reliability. It generally follows the principle of “external to internal, non-destructive to destructive”. Failure analysis is typically a multi-technique, multi-step collaborative process. The general workflow is as follows: Electrical test to locate electrical failure→ Non-destructive testing (X-Ray, C-SAM) to examine internal package conditions → Decapsulation → Optical inspection → Thermal analysis or EMMI/OBIRCH → FIB/SEM/TEM for fine structural and compositional analysis.

This is the first step and a guide to failure analysis. All subsequent physical analyses are based on the anomalies detected in the electrical test.

• Methodology: Use parameter analyzers or Automatic Test Equipment (ATE) to measure the device’s current-voltage (IV) characteristics, functional logic, port resistance/capacitance, and compare them to known good devices. This helps precisely identify areas of electrical performance failure (e.g., leakage at specific pins or failure in certain functional blocks).
• Technical Challenges: Electrical testing can identify the location of circuit failures (electrical failure points), but it does not provide direct insight into thespecific physical defects responsible for the failure. Intermittent faults, which occur sporadically, present a particular challenge as they are difficult to capture and replicate. Improper testing conditions, such as over-voltage or over-current, may inadvertently exacerbate damage to the sample.
• Issues Analyzed:Short circuits, open circuits, increased leakage current, parameter drift (e.g., threshold voltage shift), functional failure, abnormal contact resistance, gate oxide breakdown, PN junction leakage, etc.

Non-destructive testing (NDT) examines the internal structure without opening or damaging the sample, providing a foundation for any subsequent destructive analysis.

• X-Ray Inspection:
  • Methodology: X-rays are used to penetrate the sample. Different materials (e.g., silicon, metal, air) absorb X-rays to varying degrees, creating contrast differences that produce a 2D projection of the internal structure on the detector. Computed Tomography (CT) can be used for 3D reconstruction.
  • Technical Challenges: The resulting image is a 2D projection, with missing depth information, potentially causing overlapping defects that are difficult to differentiate. The resolution is limited (typically at the micron level).
  • Issues Analyzed: Wire bond integrity (breaks, lift-offs), solder ball voids, bridging, chip tilt, internal package contaminants, crack propagation paths, etc.
• Scanning Acoustic Microscope (C-SAM/SAT):
  • Methodology: High-frequency ultrasound is transmitted through the sample, and the reflection from different material interfaces (e.g., chip/adhesive/substrate) is captured to generate an image. The intensity and time difference of the reflected signals reveal the internal structural integrity.
  • Technical Challenges: Requires relatively low resolution (micron level). For complex structures or densely packed solder balls, the acoustic signal can be complicated, making image interpretation difficult. Water is usually required as a coupling medium.
  • Issues Analyzed: Internal voids, delamination (separation at interfaces), cracks, poor adhesion, chip cracks, uneven filling, etc.

• Decapsulation:
  • Methodology: Strong acids (e.g., fuming nitric acid, sulfuric acid) or plasma etching are used to selectively remove the plastic packaging, exposing the internal chip, bonding wires, and substrate pads.
  • Technical Challenges: The process is destructive and irreversible. The choice of chemicals, concentration, temperature, and time must be precisely controlled to avoid over-etching and damaging key structures (e.g., fine aluminum wires).
  • Issues Analyzed: Chip surface contamination, corrosion, scratching, bond pad detachment, wire breaks, metal layer corrosion, etc.
• Cross-Sectioning:
  • Methodology: The device or specific areas are cut, embedded, ground, and polished to prepare cross-sectional samples for observation.
  • Technical Challenges: Sample preparation is complex and requires precise defect localization. The grinding process may introduce new damage or alter the original defect. High skill from the operator is required.
  • Issues Analyzed: Interface bonding (delamination), bond pad internal structure (necking, cracks), chip adhesive layer thickness and voids, diffusion/deep junctions, gate oxide thickness, metal layer/via coverage, etc.
• Focused Ion Beam (FIB):
  • Methodology: FIB focuses on gallium (Ga) or other heavy metal ions to cut (milling) and deposit (e.g., platinum Pt) on the sample at the nanoscale. Typically combined with SEM for real-time observation during localized processing.
  • Technical Challenges: Ion beam exposure can induce lattice damage and Ga+ contamination, potentially altering the sample’s properties. Processing accuracy and control are critical, and the equipment is expensive.
  • Issues Analyzed: Site-specific cross-sectional analysis (precise observation of internal structures in specific connections or vias), circuit editing (cutting or connecting circuits), TEM sample preparation, three-dimensional reconstruction of defects, etc.

For more concealed or complex failures, more precise localization techniques are required.

• Thermal Imaging:
  • Methodology:
    • Liquid Crystal Hotspot Detection: Liquid crystals are applied to the chip’s surface. Then, when powered, abnormal hotspots will cause a phase change in the liquid crystal, creating easily detected bright spots under a polarized optical microscope.
    • Infrared Thermography: Directly captures the temperature distribution on the chip’s surface.
    • OBIRCH: Laser scanning of powered chips to monitor small changes in resistance to locate defects (sensitive to current).
  • Technical Challenges: Infrared thermography has limited spatial resolution (a few microns to tens of microns). OBIRCH requires powered samples and may not be sensitive to very high resistance or small leakage currents.
  • Issues Analyzed: Hotspot localization (short circuits, leakage points), junction temperature measurement, heat path analysis, etc.
• Emission Microscopy (EMMI)：
  • Methodology: Detects weak photon emissions from the chip when powered, identifying failure points where charge carriers undergo avalanche breakdown or recombination.
  • Technical Challenges: Requires photon emission at the defect site during power-up. Some non-light-emitting defects (e.g., some leakage defects) are not detectable. The signal is weak and can be subject to noise interference, requiring darkroom conditions.
  • Issues Analyzed: Gate oxide leakage, junction leakage, latch-up effects, ESD defects, contact hole failures, and other photon-emitting defects.

After defect localization, ultra-high-resolution equipment is needed to observe microscopic forms and composition.

• Scanning Electron Microscope (SEM) & Energy Dispersive Spectrometer (EDS)：
  • Methodology: SEM uses a focused electron beam to scan the sample and detect secondary and backscattered electrons for imaging, with a resolution down to the nanoscale. EDS is used to analyze elemental composition in microregions.
  • Technical Challenges: Samples must be conductive; otherwise, charging effects can distort imaging. Non-conductive samples require coating with gold or carbon. The equipment is expensive, and operation and maintenance are complex, requiring a high-vacuum environment.
  • Issues Analyzed: High-resolution morphology observation (nanoscale defects, cracks, step coverage), composition analysis (contaminant identification, material identification), cross-sectional structure observation, bond pad morphology, interlayer connection quality, etc.
• Transmission Electron Microscope (TEM)：
  • Methodology: TEM accelerates an electron beam to high speeds, passing it through ultra-thin (typically less than 100nm) samples to obtain projection images of atomic arrangements, allowing crystal structure analysis.
  • Technical Challenges: Sample preparation is the most difficult aspect, requiring mechanical grinding, ion thinning, and other techniques to reduce specific areas to electron-transmissible thickness, a time-consuming process that can easily introduce damage or lead to sample failure. The equipment is extremely expensive, and operator expertise is essential.
  • Issues Analyzed: Crystal defects (dislocations, stacking faults), gate oxide integrity (visualizing breakdown points), interface atomic structure, phase changes, diffusion phenomena, microscopic porosity, etc.